English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 62567/95223 (66%)
造訪人次 : 2522306      線上人數 : 38
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/70285

    題名: A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
    作者: Gao, Wan-lun;Yang, Wei-bin;Lo, Yu-lung
    貢獻者: 淡江大學電機工程學系
    關鍵詞: fractional;clock
    日期: 2009-12
    上傳時間: 2011-10-23 21:08:01 (UTC+8)
    出版者: Nanyang Technological University; IEEE Singapore Section
    摘要: Because system-on-a-chip (SOC) needs multiple clocks and mostly with 50% duty cycle in the same chip, in this paper, the new pseudo fractional-N and multiplier clock generator with low power phase combination controller and 50% duty cycle is proposed to achieve this purpose. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed fractional-N or multiplier clock frequencies with 50% duty cycle. Furthermore, the frequency of the output clock can be programmed by the low power phase combination controller. The circuits are processed in a standard 0.35μm CMOS technology, and work with a supply voltage of 3.3V. The simulation results demonstrate that the low power phase combination controller can save power dissipation from 9.7%~22.9%.
    關聯: 2009 12th International Symposium on Integrated Circuits(ISIC '09), pp.562 - 565
    顯示於類別:[電機工程學系暨研究所] 會議論文





    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋