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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70285

    Title: A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
    Authors: Gao, Wan-lun;Yang, Wei-bin;Lo, Yu-lung
    Contributors: 淡江大學電機工程學系
    Keywords: fractional;clock
    Date: 2009-12
    Issue Date: 2011-10-23 21:08:01 (UTC+8)
    Publisher: Nanyang Technological University; IEEE Singapore Section
    Abstract: Because system-on-a-chip (SOC) needs multiple clocks and mostly with 50% duty cycle in the same chip, in this paper, the new pseudo fractional-N and multiplier clock generator with low power phase combination controller and 50% duty cycle is proposed to achieve this purpose. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed fractional-N or multiplier clock frequencies with 50% duty cycle. Furthermore, the frequency of the output clock can be programmed by the low power phase combination controller. The circuits are processed in a standard 0.35μm CMOS technology, and work with a supply voltage of 3.3V. The simulation results demonstrate that the low power phase combination controller can save power dissipation from 9.7%~22.9%.
    Relation: 2009 12th International Symposium on Integrated Circuits(ISIC '09), pp.562 - 565
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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