In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETFF) is proposed. A Double-edge triggered flip-flop is able to transfer the data signal in both positive edge and negative edge of the clock signal. Therefore, a lower clock rate can be used to such flip-flops and the power consumption can be reduced as compared with single edge-triggered flip-flops. By HSPICE simulation results, the power consumption is reduced by 0.2% to 55% and power-delay-product is reduced by 2% to 74% in compared with others. In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETFF) is proposed. A Double-edge triggered flip-flop is able to transfer the data signal in both positive edge and negative edge of the clock signal. Therefore, a lower clock rate can be used to such flip-flops and the power consumption can be reduced as compared with single edge-triggered flip-flops. By HSPICE simulation results, the power consumption is reduced by 0.2% to 55% and power-delay-product is reduced by 2% to 74 % in compared with others.