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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70263


    Title: A New Low Power, High Speed Double-Edge Triggered Flip-Flop
    Authors: Wu, Chung-Lin;Yang, Wei-Bin;Rau, Jiann-Chyi;Wang, Chi-Hsiung
    Contributors: 淡江大學電機工程學系
    Keywords: double-edge triggered;low power;high speed Best Regards
    Double-edge triggered;Low power;High speed Best Regard
    Date: 2008-07
    Issue Date: 2011-10-23 21:06:43 (UTC+8)
    Abstract: In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETFF) is proposed. A Double-edge triggered flip-flop is able to transfer the data signal in both positive edge and negative edge of the clock signal. Therefore, a lower clock rate can be used to such flip-flops and the power consumption can be reduced as compared with single edge-triggered flip-flops. By HSPICE simulation results, the power consumption is reduced by 0.2% to 55% and power-delay-product is reduced by 2% to 74% in compared with others.
    In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETFF) is proposed. A Double-edge triggered flip-flop is able to transfer the data signal in both positive edge and negative edge of the clock signal. Therefore, a lower clock rate can be used to such flip-flops and the power consumption can be reduced as compared with single edge-triggered flip-flops. By HSPICE simulation results, the power consumption is reduced by 0.2% to 55% and power-delay-product is reduced by 2% to 74 % in compared with others.
    Relation: 2008亞太華人高速電路設計研討會(HSCD 2008)論文集,5頁
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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