A New Dynamic Floating Input D Flip-Flop (DFIDFF)  for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler

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Title:	A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler
Authors:	Jau, Ting-sheng;Yang, Wei-bin;Lo, Yu-lung
Contributors:	淡江大學電機工程學系
Date:	2006-12
Issue Date:	2011-10-23 21:06:31 (UTC+8)
Publisher:	IEEE
Abstract:	A new ultra low voltage dynamic floating input D flip-flop (DFIDFF) is proposed for high speed prescaler circuit. Prescaler and VCO are the main blocks that determining the speed of phase locked-loop (PLL). In this paper, a very low power-delay product divide-by 4/5 prescaler based on our DFIDFF is proposed. The prescaler implemented with 0.13 mum 1P8M N-well CMOS process with an ultra low 0.5 V power supply voltage. By HSPICE simulation results, the power-delay product (PDP) of the novel divided-by 4/5 prescaler can be reduced over 39% in comparison to conventional divided-by 4/5 prescaler. Moreover, the novel divided-by-4/5 prescaler circuit can operate at 613 MHz with the power consumption of 8.014 uW under a 0.5 V supply voltage.
Relation:	2006 The 13th IEEE International Conference onElectronics, Circuits and Systems (ICECS '06),pp.902 - 905
DOI:	10.1109/ICECS.2006.379935
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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