A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/70233

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题名:	A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
作者:	Cheng, Kuo-hsing;Yang, Wei-bin;Ying, Cheng-ming
贡献者:	淡江大學電機工程學系
日期:	2004-05
上传时间:	2011-10-23 21:04:57 (UTC+8)
出版者:	IEEE; Circuits and Systems Society
摘要:	A dual-slope frequency detector and charge pump architecture to achieve fast locking of phased-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A course-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed PLL circuit is designed based on the TSMC 0.35 μm 1P4M CMOS process with a 3.3V supply voltage. HSPICE simulation shows that the lock time of the proposed PLL can be reduced over 82% in comparison to the conventional PLL. An experimental chip was implemented and measured. The measurements results show that the propose PLL has fast locking properties.
關聯:	The 2004 International Symposium on Circuits and Systems (ISCAS '04), pp.892 - 896
DOI:	10.1109/ISCAS.2004.1328310
显示于类别:	[電機工程學系暨研究所] 會議論文

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