English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 55025/89277 (62%)
造访人次 : 10606283      在线人数 : 17
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜寻范围 查询小技巧:
  • 您可在西文检索词汇前后加上"双引号",以获取较精准的检索结果
  • 若欲以作者姓名搜寻,建议至进阶搜寻限定作者字段,可获得较完整数据
  • 进阶搜寻


    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70233


    题名: A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
    作者: Cheng, Kuo-hsing;Yang, Wei-bin;Ying, Cheng-ming
    贡献者: 淡江大學電機工程學系
    日期: 2004-05
    上传时间: 2011-10-23 21:04:57 (UTC+8)
    出版者: IEEE; Circuits and Systems Society
    摘要: A dual-slope frequency detector and charge pump architecture to achieve fast locking of phased-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A course-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed PLL circuit is designed based on the TSMC 0.35 μm 1P4M CMOS process with a 3.3V supply voltage. HSPICE simulation shows that the lock time of the proposed PLL can be reduced over 82% in comparison to the conventional PLL. An experimental chip was implemented and measured. The measurements results show that the propose PLL has fast locking properties.
    關聯: The 2004 International Symposium on Circuits and Systems (ISCAS '04), pp.892 - 896
    DOI: 10.1109/ISCAS.2004.1328310
    显示于类别:[電機工程學系暨研究所] 會議論文

    文件中的档案:

    没有与此文件相关的档案.

    在機構典藏中所有的数据项都受到原著作权保护.

    TAIR相关文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回馈