A dual-slope frequency detector and charge pump architecture to achieve fast locking of phased-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A course-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed PLL circuit is designed based on the TSMC 0.35 μm 1P4M CMOS process with a 3.3V supply voltage. HSPICE simulation shows that the lock time of the proposed PLL can be reduced over 82% in comparison to the conventional PLL. An experimental chip was implemented and measured. The measurements results show that the propose PLL has fast locking properties.
The 2004 International Symposium on Circuits and Systems (ISCAS '04), pp.892 - 896