淡江大學機構典藏:Item 987654321/70228
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    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/70228


    Title: A DFT Architecture for a Dynamic Fault Model of The Embedded Mask ROM of SOC
    Authors: Lee, Yang-han;Jan, Yih-guagn;Shen, Jei-jung;Tzeng, Shian-wei;Chuang, Ming-hsueh;Lin, Jheng-yao
    Contributors: 淡江大學電機工程學系
    Date: 2005-08
    Issue Date: 2011-10-23 21:04:39 (UTC+8)
    Publisher: MTDT
    Abstract: This paper describes a fail situation in the mass product testing of the embedded NAND-type mask ROM of a SOC "of passing in the high speed test, but fails in the low speed test", and propose a fault model of the situation. We also propose a general solution of testing to cope with this fault model. Finally, we invent DFT architecture to cover the fault model to reduce the testing time.
    Relation: 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), pp.78-82
    DOI: 10.1109/MTDT.2005.8
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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