English  |  正體中文  |  简体中文  |  Items with full text/Total items : 62793/95819 (66%)
Visitors : 3638142      Online Users : 174
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/70228


    Title: A DFT Architecture for a Dynamic Fault Model of The Embedded Mask ROM of SOC
    Authors: Lee, Yang-han;Jan, Yih-guagn;Shen, Jei-jung;Tzeng, Shian-wei;Chuang, Ming-hsueh;Lin, Jheng-yao
    Contributors: 淡江大學電機工程學系
    Date: 2005-08
    Issue Date: 2011-10-23 21:04:39 (UTC+8)
    Publisher: MTDT
    Abstract: This paper describes a fail situation in the mass product testing of the embedded NAND-type mask ROM of a SOC "of passing in the high speed test, but fails in the low speed test", and propose a fault model of the situation. We also propose a general solution of testing to cope with this fault model. Finally, we invent DFT architecture to cover the fault model to reduce the testing time.
    Relation: 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), pp.78-82
    DOI: 10.1109/MTDT.2005.8
    Appears in Collections:[電機工程學系暨研究所] 會議論文

    Files in This Item:

    There are no files associated with this item.

    All items in 機構典藏 are protected by copyright, with all rights reserved.


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback