USA:Institute of Electrical and Electronics Engineers
摘要:
A multiplying delay-locked loop (MDLL) is adopted for low-jitter clock generation. This architecture overcomes the drawback of phase-locked loops (PLL) such as jitter accumulation, and maintain the advantage of a PLL for multirate frequency multiplication. The MDLL, implemented in 90-nm CMOS technology, occupies about 1 mm2 and works at 400 MHz with multiplication ratio of 4. The complete synthesizer, including the output buffers, dissipates 31 mW from a 1.2V supply at 400 MHz. The rms jitter is 0.934 ps according to the phase noise integrated from 1 KHz to 1 MHz, when the output frequency is 400 MHz.
關聯:
The 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2010),pp.53-56