A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery

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題名:	A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery
作者:	Cheng, Kuo-Hsing;Chen, Chao-An;Yang, Wei-Bin;Cho, Feng-Hsin
貢獻者:	淡江大學電機工程學系
日期:	2007-04
上傳時間:	2011-10-23 21:04:00 (UTC+8)
出版者:	工業技術研究院（ITRI); IEEE
摘要:	In this paper, we present architecture of phase-locked loop (PLL) for clock and data recovery (CDR) for high-speed serial links. The conventional over-sampling architecture uses two timing modules. One is used to track reference clock, the other is to generate multiphase to sample high speed serial-in data. The architecture improves drawback of the conventional CDR by using Blender unit to make high resolution delay phase and PLL will track this phase. Additionally, this work achieves to save power and chip area and the stability of system can be improved, because of combining the two timing modules to one. This work is fabricated by TSMC 0.13um 1p8m 1.2v process. The PLL is operates at 500MHz and CDR circuit can recovery 5Gb/s serial-in data.
關聯:	2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2007), pp.1~4
DOI:	10.1109/VDAT.2007.373236
顯示於類別:	[電機工程學系暨研究所] 會議論文

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