A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage

doi:10.1109/ASSCC.2008.4708732

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Title:	A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage
Authors:	Liang, Yung-chih;Huang, Ching-ji;Yang, Wei-bin
Contributors:	淡江大學電機工程學系
Date:	2008-11
Issue Date:	2011-10-23 21:03:52 (UTC+8)
Publisher:	IEEE Solid-State Circuits Society (IEEE SSCS)
Abstract:	This paper presents a 0.5-V ultra-low voltage multiplier. In order to achieve ultra-low voltage and high speed operation, we modify the traditional pipelined architecture and adopt a PMOS forward body bias control technique, a symmetric signal path full-adder structure and a synchronous output D flip flop. Fabricated in 130nm CMOS technology, the measured operation rate of 8bit x 8bit pipelined multiplier get up to 320-MHz clock rate and the power consumption is about 1.48mW from 0.5-V power supply. This paper presents a 0.5-V ultra-low voltage multiplier. In order to achieve ultra-low voltage and high speed operation, we modify the traditional pipelined architecture and adopt a PMOS forward body bias control technique, a symmetric signal path full-adder structure and a synchronous output D flip flop. Fabricated in 130 nm CMOS technology, the measured operation rate of 8bit times 8bit pipelined multiplier get up to 320-MHz clock rate and the power consumption is about 1.48 mW from 0.5-V power supply.
Relation:	2008 IEEE Asian Solid-State Circuit Conference (A-SSCC '08), pp.73 - 76
DOI:	10.1109/ASSCC.2008.4708732
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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