淡江大學機構典藏:Item 987654321/68601
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    题名: MARS: aRISC-based architecture for Lisp
    作者: Lee, Hung-Chang;Lai, Feipei;Tsai, Jenn-yuan;Parng, Tai-ming
    贡献者: 淡江大學資訊管理學系
    关键词: LISP;reduced instruction set computing;special purpose computers
    日期: 1990-03
    上传时间: 2011-10-23 13:18:42 (UTC+8)
    出版者: Oxford: Pergamon
    摘要: A RISC-based chip set architecture for Lisp is presented in this paper. This architecture contains an instruction fetch unit (IFU) and three processing units—integer processing unit (IPU), floating-point processing unit (FPU), and list processing unit (LPU). The IFU feeds instructions to the processing units and supports fast procedure call/return and branch, the IPU and FPU execute operations of different data type, and the LPU handles the Lisp runtime environment, dynamic type checking, and fast list access. In this architecture, the critical path of complex register file access and ALU operation is distributed into the LPU and IPU, and the tracing of a list can be done quickly by the non-delayed car or cdr instructions of the LPU. Performance simulation shows that this architecture would be about 6.2 times faster than SPUR and about 2.2 times faster than MIPS-X.
    關聯: Engineering Applications of Artificial Intelligence 3(1), pp.19-29
    DOI: 10.1016/0952-1976(90)90018-H
    显示于类别:[資訊管理學系暨研究所] 期刊論文

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