淡江大學機構典藏:Item 987654321/68451
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    题名: Optimization on instruction reorganization
    作者: Lai, F.;李鴻璋;Lee, H. C.;Lee, C. L.
    贡献者: 淡江大學資訊管理學系
    日期: 1990-11
    上传时间: 2011-10-23 12:57:07 (UTC+8)
    出版者: IEEE
    摘要: A pipelined processor increases its performance by partitioning an instruction into several separate operation steps. Several instructions can be executed in the pipeline in different pipe stages at the same time. Because of the overlapped execution of instructions, the result of an instruction may be used before it is available. One way to solve this problem is to schedule instructions at compiler time, thus the codes generated will be free from interlocks. The scheduling algorithm presented by T. Gross (1983) and J. Hennessy and T. Gross (1983) had significantly reduced the pipeline interlocks. With some modifications to distinguish the conflict condition, the algorithm does better at the same cost.
    關聯: 1990 ACM & IEEE the 23rd international symposium and workshop on Microprogramming and Microarchitecture(Micro-23), pp.143-148
    DOI: 10.1109/MICRO.1990.151436
    显示于类别:[資訊管理學系暨研究所] 會議論文

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