English  |  正體中文  |  简体中文  |  Items with full text/Total items : 51511/86795 (59%)
Visitors : 8281237      Online Users : 98
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/68451


    Title: Optimization on instruction reorganization
    Authors: Lai, F.;李鴻璋;Lee, H. C.;Lee, C. L.
    Contributors: 淡江大學資訊管理學系
    Date: 1990-11
    Issue Date: 2011-10-23 12:57:07 (UTC+8)
    Publisher: IEEE
    Abstract: A pipelined processor increases its performance by partitioning an instruction into several separate operation steps. Several instructions can be executed in the pipeline in different pipe stages at the same time. Because of the overlapped execution of instructions, the result of an instruction may be used before it is available. One way to solve this problem is to schedule instructions at compiler time, thus the codes generated will be free from interlocks. The scheduling algorithm presented by T. Gross (1983) and J. Hennessy and T. Gross (1983) had significantly reduced the pipeline interlocks. With some modifications to distinguish the conflict condition, the algorithm does better at the same cost.
    Relation: 1990 ACM & IEEE the 23rd international symposium and workshop on Microprogramming and Microarchitecture(Micro-23), pp.143-148
    DOI: 10.1109/MICRO.1990.151436
    Appears in Collections:[資訊管理學系暨研究所] 會議論文

    Files in This Item:

    There are no files associated with this item.

    All items in 機構典藏 are protected by copyright, with all rights reserved.


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback