Multiprocessor architecture reconciling symbolic with numerical processing

淡江大學機構典藏 > 商管學院 > 資訊管理學系暨研究所 > 會議論文 > Item 987654321/68446

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題名:	Multiprocessor architecture reconciling symbolic with numerical processing
作者:	Jang, G. S.;Lai, F.;李鴻璋;Lee, H. C.;Maa, Y. C.;Parng, T. M.;Tsai, J. Y.
貢獻者:	淡江大學資訊管理學系
日期:	1989-05
上傳時間:	2011-10-23 12:56:48 (UTC+8)
出版者:	IEEE
摘要:	The design of CPU (central processing unit) chips for the MARS project is described. They are the IFU (instruction fetch unit), IPU (integer processing unit), and LPU (list processing unit). The IFU is devised to interleave instruction fetch and execution, and thus to achieve coordinated execution among datapath chips. The IPU is the main computing engine for integer operations and operand address calculation. By using dual-instruction buffers, a reserved phase for branch/jump target fetch, and instruction decode peeping, the architecture can support almost-zero-delay branching and super-zero-delay jump. The LPU handles a Lisp runtime environment, dynamic type checking, and fast list access. In this architecture, the critical path of complex register file access and ALU operation is distributed over the LPU and IPU, and list tracing can be executed quickly by the nondelayed car or cdr instructions.
關聯:	International symposium on VLSI technology, system and applications, pp.365-370
DOI:	10.1109/VTSA.1989.68647
顯示於類別:	[資訊管理學系暨研究所] 會議論文

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