| Title: | Power-aware compression scheme for multiple scan-chain |
| Authors: | Rau, Jiann-Chyi;Wu, Po-Han |
| Contributors: | 淡江大學電機工程學系 |
| Keywords: | scan based testing;low power testing;test data compression;design for testability (DfT) |
| Date: | 2011-06 |
| Issue Date: | 2011-10-15 01:17:53 (UTC+8) |
| Publisher: | Abingdon: Taylor & Francis Ltd. |
| Abstract: | As test data continues to grow quickly, test cost also increases. For the sake of decreasing the test cost, this article presents a new data dependency compression scheme for large circuit which is based on multiple scan chains. We propose new compression architecture with fixed length for running tests. In results, when the complexity of a VLSI circuit is growing, the number of input pins for testing is very low. Since test data in power aware is not changed frequently, we use a selector to filter the unnecessary status and buffers to hold the back data. We also propose a new algorithm to assign multiple scan chains and an improved linear dependency compute method to find the hidden dependency between scan chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power. |
| Relation: | Journal of the Chinese Institute of Engineers 34(4), pp.515-527 |
| DOI: | 10.1080/02533839.2011.576498 |
| Appears in Collections: | [電機工程學系暨研究所] 期刊論文
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