Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment

doi:10.1049/iet-cdt.2009.0115

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Title:	Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment
Authors:	Rau, Jiann-Chyi;Wu, Po-Han
Contributors:	淡江大學電機工程學系
Date:	2011-01
Issue Date:	2011-10-15 01:17:40 (UTC+8)
Publisher:	Stevenage: The Institution of Engineering and Technology
Abstract:	As the test data continues to grow quickly, test cost also increased. For the sake of decreasing the test cost, this study presents a new compression for large circuit, which is based on multiple scan-chains and unknown structure. The proposed method is targeted at intellectual property cores and system-on-a-chip. The authors consider the shift-in power and compression ratio in low-cost automatic test equipment (ATE) environment. A new compression architecture with fixed length for running ones is proposed. For the proposed method, the ATE has no repeated function and synchronisation signal. In the results, when the complexity of very large-scale integrated circuit is growing up, the number of input pins for testing is very low. The average compression ratio of our method is 63% for MinTest and TetraMAX on ISCAS'89 benchmarks. The average of peak/weight transition count shift-in turns to 3x/6.6x for MinTest and 2.3x/5.6x for TetraMAX, after comparing selective scan slice and the proposed method. The average of hardware overhead is 6% for MinTest and 6.5% for TetraMAX.
Relation:	IET Computers & Digital Techniques 5(1), pp.25-35
DOI:	10.1049/iet-cdt.2009.0115
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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