An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/61038

請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/61038

題名:	An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
作者:	Rau, Jiann-Chyi;Wu, Chung-Lin;Wu, Po-Han
貢獻者:	淡江大學電機工程學系
關鍵詞:	Clock Gating;Scan Test;Low Power Scan Test;Full-Scan Testing;Design for Testability;Yield Loss
日期:	2011-03-01
上傳時間:	2011-10-15 01:17:16 (UTC+8)
出版者:	新北市：淡江大學
摘要:	Recently, power dissipation in full-scan testing has brought a great challenge for test engineers. In addition to shift power reduction, excessive switching activity during capture operation may lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response per capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time. Experimental results for ISCAS'89 benchmark circuits show that the capture power reduction in test sequence can up to 55%.
關聯:	Tamkang Journal of Science and Engineering=淡江理工學刊 14(1), pp.39-48
DOI:	10.6180/jase.2011.14.1.06
顯示於類別:	[電機工程學系暨研究所] 期刊論文

文件中的檔案:

檔案	描述	大小	格式	瀏覽次數
1560-6686_14(1)p39-48.pdf		3707Kb	Adobe PDF	308	檢視/開啟

在機構典藏中所有的資料項目都受到原著作權保護.

TAIR相關文章