Hardware/software co-design for particle swarm optimization algorithm

doi:10.1016/j.ins.2010.07.017

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/61031

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题名:	Hardware/software co-design for particle swarm optimization algorithm
作者:	Li, Shih-An;Hsu, Chen-Chien;Wong, Ching-Chang;Yu, Chia-Jun
贡献者:	淡江大學電機工程學系
关键词:	HW/SW co-design;Particle swarm optimization (PSO);System on a programmable chip (SOPC);Field Programmable Gate Array (FPGA)
日期:	2011-10
上传时间:	2011-10-15 01:16:36 (UTC+8)
出版者:	Philadelphia: Elsevier Inc.
摘要:	This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve design flexibility and execution performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a Particle Updating Accelerator module via hardware implementation for updating velocity and position of particles and a Fitness Evaluation module implemented either on a soft-cored processor or Field Programmable Gate Array (FPGA) for evaluating the objective functions are respectively designed to work closely together to carry out the evolution process at different design stages. Thanks to the design flexibility, the proposed approach can tackle various optimization problems of embedded applications without the need for hardware redesign. To further improve the execution performance of the PSO, a hardware random number generator (RNG) is also designed in this paper in addition to a particle re-initialization scheme to promote exploration search during the optimization process. Experimental results have demonstrated that the proposed HW/SW co-design approach for PSO algorithms has good efficiency for obtaining high-quality solutions for embedded applications.
關聯:	Information Sciences 181(20), pp.4582–4596
DOI:	10.1016/j.ins.2010.07.017
显示于类别:	[電機工程學系暨研究所] 期刊論文

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