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    題名: A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output
    作者: Yang, Wei-Bin;Lo, Yu-Lung;Chao, Ting-Sheng
    貢獻者: 淡江大學電機工程學系
    關鍵詞: fractional-N;clock generator;pseudo fractional-N controller;duty cycle
    日期: 2010-03
    上傳時間: 2011-10-15 01:11:59 (UTC+8)
    出版者: Tokyo: Denshi Jouhou Tsuushin Gakkai
    摘要: A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13 μm CMOS technology, and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146 μW at 304 MHz.
    關聯: IEICE Transactions on Electronics E93-C(3), pp.309-316
    DOI: 10.1587/transele.E93.C.309
    顯示於類別:[電機工程學系暨研究所] 期刊論文

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