English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 52068/87197 (60%)
造访人次 : 8906925      在线人数 : 523
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜寻范围 查询小技巧:
  • 您可在西文检索词汇前后加上"双引号",以获取较精准的检索结果
  • 若欲以作者姓名搜寻,建议至进阶搜寻限定作者字段,可获得较完整数据
  • 进阶搜寻


    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60986


    题名: A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output
    作者: Yang, Wei-Bin;Lo, Yu-Lung;Chao, Ting-Sheng
    贡献者: 淡江大學電機工程學系
    关键词: fractional-N;clock generator;pseudo fractional-N controller;duty cycle
    日期: 2010-03
    上传时间: 2011-10-15 01:11:59 (UTC+8)
    出版者: Tokyo: Denshi Jouhou Tsuushin Gakkai
    摘要: A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13 μm CMOS technology, and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146 μW at 304 MHz.
    關聯: IEICE Transactions on Electronics E93-C(3), pp.309-316
    DOI: 10.1587/transele.E93.C.309
    显示于类别:[電機工程學系暨研究所] 期刊論文

    文件中的档案:

    档案 描述 大小格式浏览次数
    0916-8524_E93.C(3)p309-316.pdf7083KbAdobe PDF5检视/开启

    在機構典藏中所有的数据项都受到原著作权保护.

    TAIR相关文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回馈