淡江大學機構典藏:Item 987654321/60960
English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 58605/92268 (64%)
造訪人次 : 550860      線上人數 : 59
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60960


    題名: High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
    作者: Lo, Yu-lung;Yang, Wei-bin;Chao, Ting-sheng;Cheng, Kuo-hsing
    貢獻者: 淡江大學電機工程學系
    關鍵詞: dynamic D flip-flops;counters;prescalers;ultra-low-voltage design
    日期: 2009-06
    上傳時間: 2011-10-15 01:09:33 (UTC+8)
    出版者: Tokyo: Denshi Jouhou Tsuushin Gakkai
    摘要: A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-μm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600MHz and 8.35μW at a 0.5V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang’s counter [1], and the E-TSPC counter [2], respectively.
    關聯: IEICE Transactions on Electronics E92-C(6), pp.890-893
    DOI: 10.1587/transele.E92.C.890
    顯示於類別:[電機工程學系暨研究所] 期刊論文

    文件中的檔案:

    沒有與此文件相關的檔案.

    在機構典藏中所有的資料項目都受到原著作權保護.

    TAIR相關文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋