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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60960

    Title: High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
    Authors: Lo, Yu-lung;Yang, Wei-bin;Chao, Ting-sheng;Cheng, Kuo-hsing
    Contributors: 淡江大學電機工程學系
    Keywords: dynamic D flip-flops;counters;prescalers;ultra-low-voltage design
    Date: 2009-06
    Issue Date: 2011-10-15 01:09:33 (UTC+8)
    Publisher: Tokyo: Denshi Jouhou Tsuushin Gakkai
    Abstract: A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-μm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600MHz and 8.35μW at a 0.5V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang’s counter [1], and the E-TSPC counter [2], respectively.
    Relation: IEICE Transactions on Electronics E92-C(6), pp.890-893
    DOI: 10.1587/transele.E92.C.890
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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