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    题名: High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
    作者: Lo, Yu-lung;Yang, Wei-bin;Chao, Ting-sheng;Cheng, Kuo-hsing
    贡献者: 淡江大學電機工程學系
    关键词: dynamic D flip-flops;counters;prescalers;ultra-low-voltage design
    日期: 2009-06
    上传时间: 2011-10-15 01:09:33 (UTC+8)
    出版者: Tokyo: Denshi Jouhou Tsuushin Gakkai
    摘要: A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-μm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600MHz and 8.35μW at a 0.5V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang’s counter [1], and the E-TSPC counter [2], respectively.
    關聯: IEICE Transactions on Electronics E92-C(6), pp.890-893
    DOI: 10.1587/transele.E92.C.890
    显示于类别:[電機工程學系暨研究所] 期刊論文

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