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    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60953

    题名: The Efficient TAM Design for Core-Based SOCs Testing
    作者: Rau, Jiann-chyi;Wu, Po-han;Chien, Chih-lung;Wu, Chien-hsu
    贡献者: 淡江大學電機工程學系
    关键词: SOC Testing;TAM;Testing Scheduling
    日期: 2008-11
    上传时间: 2011-10-15 01:08:47 (UTC+8)
    出版者: Athens: World Scientific and Engineering Academy and Society (W S E A S)
    摘要: This paper presents a framework and an efficient method to determine SOC test schedules. We increase the test TAM widths by the framework. Our method deals with the traditional scan chains and reconfigurable multiple scan chains. Experimental results for ITC’02 SOC TEST Benchmarks show that we obtain better test application time when compared to previously published algorithms. Test access mechanism (TAM) and test schedule for System-On-chip (SOC) are challenging problems. Test schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a core section method based on generalized 2-D rectangle packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test.
    關聯: WSEAS Transactions on Circuits And Systems 11(7), pp.922-931
    显示于类别:[電機工程學系暨研究所] 期刊論文





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