淡江大學機構典藏:Item 987654321/60942
English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 62805/95882 (66%)
造访人次 : 3910809      在线人数 : 359
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜寻范围 查询小技巧:
  • 您可在西文检索词汇前后加上"双引号",以获取较精准的检索结果
  • 若欲以作者姓名搜寻,建议至进阶搜寻限定作者字段,可获得较完整数据
  • 进阶搜寻


    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/60942


    题名: An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
    作者: Rau, Jiann-chyi;Wu, Po-han;Ma, Jia-shing
    贡献者: 淡江大學電機工程學系
    关键词: SOC;Testing;TAM
    日期: 2008-06
    上传时间: 2011-10-15 01:07:47 (UTC+8)
    出版者: Zographou: World Scientific and Engineering Academy and Society (W S E A S)
    摘要: In recent years the advance of CMOS technology has led to a great development, especially on the complexity of the system-on-chip (SOC). As the development of circuit with different technology, the embedded cores embedded into system-on-chips (SOCs) usually have multi-frequency to drive it. In this paper, we present a heuristic approach of TAM optimization according to the reality and reduce the test application time. The proposed method is applicable to the design model with hierarchy SOCs. We pay the price in hardware overhead in order to decrease test application time.
    關聯: WSEAS Transactions on Circuits And System 6(7), pp.558-568
    显示于类别:[電機工程學系暨研究所] 期刊論文

    文件中的档案:

    档案 描述 大小格式浏览次数
    1109-2734_6(7)p558-568.pdf455KbAdobe PDF171检视/开启

    在機構典藏中所有的数据项都受到原著作权保护.

    TAIR相关文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回馈