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    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/60894


    Title: Concurrent bit-plane coding architecture for EBCOT in JPEG2000
    Authors: 簡丞志
    Contributors: 淡江大學電機工程學系
    Keywords: Image coding;Computer architecture;Context modeling;Concurrent computing;Discrete wavelet transforms;Quantization;Arithmetic;Transform coding;Propagation losses;Clocks
    Date: 2006-09-11
    Issue Date: 2011-10-15 01:03:07 (UTC+8)
    Abstract: This work presents a concurrent bit-plane coding architecture for EBCOT of JPEG2000. The architecture uses two bit-planes at the same time to encode data and this scheme can reduce the requirement of internal memory efficiently. Compared with the conventional approach, our concurrent architecture can save 8K-bit internal memory. In our proposed architecture, it can process data as long as the data of the two bit-planes are available, and at the same time the system can keep reading data from the external memory. This approach can increase the computation efficiency and avoid the waiting time for reading external data. It can also reduce the access times of the internal memory. Compared with the conventional context modeling architecture, the proposed concurrent bit-plane coding architecture can reduce the computation time by more than 50%
    This work presents a concurrent bit-plane coding architecture for EBCOT of JPEG2000. The architecture uses two bit-planes at the same time to encode data and this scheme can reduce the requirement of internal memory efficiently. Compared with the conventional approach, our concurrent architecture can save 8K-bit internal memory. In our proposed architecture, it can process data as long as the data of the two bit-planes are available, and at the same time the system can keep reading data from the external memory. This approach can increase the computation efficiency and avoid the waiting time for reading external data. It can also reduce the access times of the internal memory. Compared with the conventional context modeling architecture, the proposed concurrent bit-plane coding architecture can reduce the computation time by more than 50%
    Relation: 2006 IEEE International Symposium on Circuits and Systems, p.4595-4598
    DOI: 10.1109/ISCAS.2006.1693653
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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