Design of an Adjustable-way Cache for Energy Reduction

doi:10.1080/02533839.2005.9671036

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/60874

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題名:	Design of an Adjustable-way Cache for Energy Reduction
作者:	Chen, Hsin-chuan;Chiang, Jen-shiun
貢獻者:	淡江大學電機工程學系
關鍵詞:	Associativity;Adjustable-way;Average energy dissipation;Multiprocessor systems
日期:	2005-07
上傳時間:	2013-07-11 11:57:06 (UTC+8)
出版者:	Taipei : Chinese Institute of Chemical Engineers
摘要:	Conventional set‐associative caches, with higher associativity, provide lower miss rates. However, they suffer from longer hit access time and larger energy dissipation. Based on the consideration of different program localities, programs should have their own appropriate associativity of caches. In this paper, we propose a set‐associative cache that can provide flexibilities to adjust its associativity according to different program behaviors, which means that the proposed cache scheme can be adjusted from an n‐way set‐associative cache to a direct‐mapped cache. By use of this cache architecture, power consumption can be lowered when an n‐way set‐associative cache configures the cache with lower associativity (less than n) due to only enabling fewer subarrays of the tag memory and data memory. However, the performance is still maintained at the same level as in a conventional set‐associative cache or direct‐mapped cache. Adjustable‐way set‐associative caches can also be applied to multiprocessor systems to reduce the average, overall system, energy dissipation.
關聯:	Journal of the Chinese Institute of Engineers=中國工程學刊 28(4), pp. 691- 700
DOI:	10.1080/02533839.2005.9671036
顯示於類別:	[電機工程學系暨研究所] 期刊論文

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