A low-jitter phase-interpolation DDS using dual-slope integration

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/60847

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題名:	A low-jitter phase-interpolation DDS using dual-slope integration
作者:	Chen, Hsin-chuan;江正雄;Chiang, Jen-shiun
貢獻者:	淡江大學電機工程學系
關鍵詞:	phase-interpolation DDS;dual-slope integration;capacitance error;delay time error
日期:	2004-09-25
上傳時間:	2011-10-15 00:58:33 (UTC+8)
摘要:	In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide positive-slope integration on an integration capacitor in the first phase, and then performs negative-slope integration operation on the same integration capacitor in the second phase. By using dual-slope integration on a single capacitor, the delay time error caused by capacitance error can be avoided and the die size can be reduced in circuit implementation. Therefore, the proposed DDS without ROM tables can achieve a low-jitter clock output due to generating the more precise delay time.
關聯:	IEICE Electronics Express 1(12), pp.333-338
DOI:	10.1587/elex.1.333
顯示於類別:	[電機工程學系暨研究所] 期刊論文

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