A low-jitter phase-interpolation DDS using dual-slope integration

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/60847

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Title:	A low-jitter phase-interpolation DDS using dual-slope integration
Authors:	Chen, Hsin-chuan;江正雄;Chiang, Jen-shiun
Contributors:	淡江大學電機工程學系
Keywords:	phase-interpolation DDS;dual-slope integration;capacitance error;delay time error
Date:	2004-09-25
Issue Date:	2011-10-15 00:58:33 (UTC+8)
Abstract:	In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide positive-slope integration on an integration capacitor in the first phase, and then performs negative-slope integration operation on the same integration capacitor in the second phase. By using dual-slope integration on a single capacitor, the delay time error caused by capacitance error can be avoided and the die size can be reduced in circuit implementation. Therefore, the proposed DDS without ROM tables can achieve a low-jitter clock output due to generating the more precise delay time.
Relation:	IEICE Electronics Express 1(12), pp.333-338
DOI:	10.1587/elex.1.333
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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