A Radix-4 New Svota-Tung Divider with Constant Timing Complexity for Precsaling

doi:10.1023/A:1021150020008

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/60812

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題名:	A Radix-4 New Svota-Tung Divider with Constant Timing Complexity for Precsaling
作者:	江正雄;Chiang, Jen-shiun;Tsai, Min-show
貢獻者:	淡江大學電機工程學系
關鍵詞:	computer arithmetic;floating-point division;new Svoboda-Tung;division;prescaling;radix-4;signed digit number system;Svoboda-Tung division
日期:	2003-01
上傳時間:	2011-10-15 00:55:09 (UTC+8)
摘要:	A new floating-point division architecture that complies with the IEEE 754-1985 standard is proposed in this paper. This architecture is based on the New Svoboda-Tung (NST) division algorithm and the radix-4 MROR (maximally redundant maximally recoded) signed digit number system. In NST division, the divisor and dividend must be prescaled. We summarize a general systematic method to accomplish the prescaling, and we also propose a hardware scheme such that the timing complexity is constant regardless of the bit length of the divisor. For the divider implementation, a new MROR signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. A 32-b/32-b radix-4 divider is thus designed in Verilog HDL; the simulation results show that this architecture is implementable using currently available libraries. The hardware complexity and performance of this divider is competitive with conventional SRT dividers.
關聯:	Kluwer Journal of VLSI Signal Processing 33(1/2), pp.117-124
DOI:	10.1023/A:1021150020008
顯示於類別:	[電機工程學系暨研究所] 期刊論文

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