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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60809

    Title: Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm
    Authors: Kuo, Chien-hung;Hsueh, Tzu-chien;Liu, Shen-iuan
    Contributors: 淡江大學電機工程學系
    Date: 2002-12-01
    Issue Date: 2011-10-15 00:54:53 (UTC+8)
    Publisher: New York: Springer New York LLC
    Abstract: A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is −7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.
    Relation: Analog Integrated Circuits and Signal Processing 33(3), pp.289-300
    DOI: 10.1023/A:1020769913779
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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