A timing driven pseudo exhaustive testing for VLSI circuits

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/60771

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题名:	A timing driven pseudo exhaustive testing for VLSI circuits
作者:	Chang, Shih-chieh;饒建奇;Rau, Jiann-chyi
贡献者:	淡江大學電機工程學系
日期:	2001-01-01
上传时间:	2011-10-15 00:51:09 (UTC+8)
摘要:	Because of its ability to detect all nonredundant combinational faults, exhaustive testing, which applies all possible input combinations to a circuit, is an attractive test method. However, the test application time for exhaustive testing can be very large. To reduce the test time, pseudoexhaustive testing inserts some bypass storage cells (bscs) so that the dependency of each node is within some predetermined value. Though bsc insertion can reduce the test time, it may increase circuit delay, In this paper, our objective is to reduce the delay penalty of bsc insertion for pseudoexhaustive testing. We first propose a tight delay lower bound algorithm, which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, ne can propose a bsc insertion heuristic that tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.
關聯:	Computer-Aided design of integrated circuits and systems 20(1), pp.147-158
DOI:	10.1109/43.905682
显示于类别:	[電機工程學系暨研究所] 期刊論文

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