Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits

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Title:	Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
Authors:	Rau, Jiann-chyi;Jone, W.B.;Chang, S.C.;Wu, Y.L.
Contributors:	淡江大學電機工程學系
Date:	2000-10
Issue Date:	2011-10-15 00:50:47 (UTC+8)
Publisher:	The Institution of Engineering and Technology(IET)
Abstract:	A new test architecture, called TLS (tree-LFSR/SR), generates pseudo-exhaustive test patterns for both combinational and sequential VLSI circuit is presented. Instead of using a single scan chain, the proposed test architecture routes a scan tree driven by the LFSR to generate all possible input patterns for each output cone. The new test architecture is able to take advantages of both signal sharing and signal reuse. The benefits are: the difficulty of test architecture synthesis can be eased by accelerating the searching process of appropriate residues; and the number of XOR gates to satisfy the pseudo-exhaustive test criterion can be reduced. The TLS test scheme mainly contains three phases: backbone generation, tree growing, and XOR-tree generation. Experimental results obtained by simulating combinational and sequential benchmark circuits are very encouraging
Relation:	IEE Proceedings - Computers and Digital Techniques 147(5), pp.343-348
DOI:	10.1049/ip-cdt:20000544
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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