Latched CMOS differential logic(LCDL)for complex high-speed VLSI

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/60698

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題名:	Latched CMOS differential logic(LCDL)for complex high-speed VLSI
作者:	Wu, Chung-yu;鄭國興;Cheng, Kuo-hsing
貢獻者:	淡江大學電機工程學系
關鍵詞:	CMOS logic circuits;Very large scale integration;Clocks;Logic functions;Logic circuits;Switches;Pipelines;Voltage;MOS devices;Power dissipation
日期:	1991-09
上傳時間:	2011-10-15 00:44:09 (UTC+8)
摘要:	A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL.
關聯:	IEEE Journal of Solid-State Circuits 26(9), p.1324-1328
DOI:	10.1109/4.84952
顯示於類別:	[電機工程學系暨研究所] 期刊論文

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