A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL.
Relation:
IEEE Journal of Solid-State Circuits 26(9), p.1324-1328
