Synthesizing nested loop algorithms using nonlinear transformation method

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Title:	Synthesizing nested loop algorithms using nonlinear transformation method
Authors:	張志勇;Chang, Chih-yung;Sheu, J.P.
Contributors:	淡江大學資訊工程學系
Keywords:	Data dependence;hyperplane method;nested For-loops;parallel processing;systolic arrays
Date:	1991-07
Issue Date:	2011-10-05 22:32:12 (UTC+8)
Publisher:	Piscataway: Institute of Electrical and Electronics Engineers
Abstract:	FOR-loops are the main source of parallelism in programs. A nonlinear transformation algorithm for parallelizing the execution of FOR-loop models is proposed. It is shown that by the mapping of nonlinear transformation, iterations of FOR-loops can be executed in a parallel form. The algorithm is useful in exploiting the parallelism of FOR-loops with one or more partitions on the innermost loop. Algorithms to partition and map the nested FOR-loops onto fixed size systolic arrays are discussed. Based on the time and space mapping schemes, all the iterations of FOR-loops can be correctly executed on the array processors in a parallel form
Relation:	IEEE Transactions on Parallel and Distributed Systems 2(3), pp.304-317
DOI:	10.1109/71.86106
Appears in Collections:	[Graduate Institute & Department of Computer Science and Information Engineering] Journal Article

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