English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 51510/86705 (59%)
造訪人次 : 8271764      線上人數 : 104
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/59928

    題名: Improving memory traffic by assembly-level exploitation of reuses for vector registers
    作者: Chang, Chih-yung;Chen, T. S.;Sheu, J. P.
    貢獻者: 淡江大學資訊工程學系
    關鍵詞: data dependence;vector register;partial reuse;vector compilers;reuse distance;vectorization;supercomputer
    日期: 2000-09-01
    上傳時間: 2011-10-05 22:27:50 (UTC+8)
    摘要: In this paper, we propose a compilation scheme to analyze and exploit the implicit reuses of vector register data. According to the reuse analysis, we present a translation strategy that translates the vectorized loops into assembly vector codes with exploitation of vector reuses. Experimental results show that our compilation technique can improve the execution time and traffic between shared memory and vector registers. Techniques discussed here are simple, systematic, and easy to be implemented in the conventional vector compilers or translators to enhance the data locality of vector registers.
    關聯: The journal of supercomputing 17(2), pp.187-204
    DOI: 10.1023/A:1008134522009
    顯示於類別:[資訊工程學系暨研究所] 期刊論文





    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋