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    題名: A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process
    作者: Yang, Wei-Bin;Liao, Chao-Cheng;Liang, Yung-Chih
    貢獻者: 淡江大學電機工程學系
    關鍵詞: Pipelined multiplier;Forward body bias;Modified full adder;New D flip-flop
    日期: 2011-01
    上傳時間: 2011-08-09 23:06:52 (UTC+8)
    出版者: London: Elsevier Ltd
    摘要: This paper presents an 8x8bit pipelined multiplier operating at 320MHz under 0.5V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5V. The proposed pipelined multiplier is fabricated in 130nm CMOS process. It operates up to 320MHz and the power consumption is only 1.48mW at 0.5V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5V is reduced over 5.7 times than that of the traditional architecture at 1.2V. Thus, the proposed 8x8bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.
    關聯: Microelectronics Journal 42(1), pp.43–51
    DOI: 10.1016/j.mejo.2010.09.005
    顯示於類別:[電機工程學系暨研究所] 期刊論文

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