16x16位元非同步管線式系統之布式乘法器

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Title:	16x16位元非同步管線式系統之布式乘法器
Other Titles:	The design of 16x16 bit booth multiplier with asynchronous pipeline technique
Authors:	何孟軒;Ho, Meng-Hsuan
Contributors:	淡江大學電機工程學系碩士班江正雄;Chiang, Jen-Shiun
Keywords:	乘法器;非同步;管線式系統;Booth Multiplier;asynchronous;Pipeline System
Date:	2011
Issue Date:	2011-06-16 22:10:16 (UTC+8)
Abstract:	算術邏輯單元(ALU)及乘法器為中央處理器（CPU）核心元件，負責所有的運算，是中央處理器主要消耗功率元件之一，降低此二部分功率消耗，可有助於降低中央處理器功率消耗。管線式結構是一種最常應用在高速運算的方式。管線式結構之所以可以達到高速運算是因為其允許每一級的運算皆採同時執行。未來，矽製程漸漸的縮小，而晶片的線路漸漸變多變複雜時，在同步系統中有兩個問題會變的越來越嚴重。即時脈網路會帶來大量的功率消耗，和時脈歪斜導致邏輯電路解出錯誤的值。有一種不一樣的電路需要被設計來解決同步系統中的兩個大問題。因此同步系統被轉換成非同步系統。在非同步的系統中，時脈網路被交握式電路給取代，藉以管理管線的運行。在本論文中，我們應用 TSMC 0.35 去模擬乘法器之核心元件：使用一種非同步系統的穩健交握式結構。來設計1616位元非同步管線式系統之布式乘法器(Booth)，為了使其運算速度提升，布斯乘法器(Booth Multiplier)，並以管線式系統的方式來實現這個非同步布式乘法器(Booth)。 Arithmetic logic unit and multiplier for the CPU core component, responsible for all operations, the central processor is one of power consumption components to reduce power consumption of this two parts, can reduce CPU power consumption. Pipeline structure is a common way used in high-speed operation. In the synchronous system, there are two problems Clock network will bring a lot of power consumption and clock skew causes Solve the wrong logic value. There is a different circuit needs to be designed to solve the synchronization system The two major problems. Therefore synchronization system is converted into Asynchronous system. In the asynchronous system In the clock network is to replace the handshake circuit in order to manage the operation of the pipeline. In this paper, we apply the TSMC 0.35 to simulate the multiplier core components: use of a robust system of non-synchronous handshaking structure. To design 16 16-bit asynchronous pipelined multiplier for distributed systems to improve computing speed, Booth multipliers, and pipeline systems approach to achieve this non-synchronous distributed multiplier.
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Thesis

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