在本論文中，我們應用 TSMC 0.35 去模擬乘法器之核心元件：使用一種非同步系統的穩健交握式結構。來設計16*16位元非同步管線式系統之布式乘法器(Booth)，為了使其運算速度提升，布斯乘法器(Booth Multiplier)，並以管線式系統的方式來實現這個非同步布式乘法器(Booth)。 Arithmetic logic unit and multiplier for the CPU core component, responsible for all operations, the central processor is one of power consumption components to reduce power consumption of this two parts, can reduce CPU power consumption.
Pipeline structure is a common way used in high-speed operation. In the synchronous system, there are two problems Clock network will bring a lot of power consumption and clock skew causes Solve the wrong logic value. There is a different circuit needs to be designed to solve the synchronization system The two major problems. Therefore synchronization system is converted into Asynchronous system. In the asynchronous system In the clock network is to replace the handshake circuit in order to manage the operation of the pipeline.
In this paper, we apply the TSMC 0.35 to simulate the multiplier core components: use of a robust system of non-synchronous handshaking structure. To design 16 * 16-bit asynchronous pipelined multiplier for distributed systems to improve computing speed, Booth multipliers, and pipeline systems approach to achieve this non-synchronous distributed multiplier.