應用於ECG量測之低功率12-Bit SAR-ADC

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 學位論文 > Item 987654321/54206

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题名:	應用於ECG量測之低功率12-Bit SAR-ADC
其它题名:	12-Bit low power SAR-ADC for ECG application
作者:	蕭名開;Hsiao, Ming-Kai
贡献者:	淡江大學電機工程學系碩士在職專班江正雄;Chiang, Jen-Shiun
关键词:	類比數位轉換器;逐漸趨近式;SAR-ADC
日期:	2011
上传时间:	2011-06-16 22:10:08 (UTC+8)
摘要:	隨著時代的演進、科技的日新月異。在現今微電腦系統、VLSI以及DSP(數位信號處理)技術的發展影響下，數位類比資料轉換器(Analog to Digital Converter 簡稱ADC or A/D轉換器)的應用已經十分的廣泛。因此針對A/D轉換器規格的需求只會越來越嚴謹，如此一來也成為了業界、學術界所積極研究探討的領域。　　為了讓A/D轉換器的應用更為廣泛並且符合現今資訊產品的需求，我們所關心的方向不外乎是A/D轉換器的速度（Speed）、解析度(Resolution)、功耗(Power)以及面積(Area)。但在許多現實條件的限制下，並沒有一個A/D轉換器能夠在設計上完全考量到上述的條件，往往只能針對應用上做出取捨。　　本論文所提出的12-Bit SAR ADC主要是應用在心電圖（ECG or EKG）量測的系統上。為了達到長時間的監控及記錄心電圖，來捕捉心率不整的頻率發生，因此規格上所制訂的電壓為1伏特（Voltage），來達到低功耗的需求。實現上，以TSMC 0.18μm 1P6M 標準製程來實現電路，其工作電壓為1V，頻寬為150Hz，取樣頻率為600Hz，當輸入訊號為24Hz時，所得信號雜訊失真比為67.53dB，有效位元為10.92bit，總消耗功率為20.28μW。 With the constant improvement on highly advanced technology nowadays, under the development of the microcomputer system, Very Large Scale Integrated circuit (VLSI) and Digital Signal Processing (DSP) influence, Analog to Digital Converter (ADC) has become a widely used application. The request for ADC specification will therefore be strict, as a result, more research will be conducted aggressively in the industrial and academic field. In order for ADC application become extensively used and correspond to the requirement of the present electronic products, four conditions need to be concerned: Speed, Resolution, Power, and Area. However, under the restriction of the factual conditions, in the process of designing, none of the ADC models was able to entirely correspond to the four conditions, thus trade-off was made for several application. This thesis refers to the 12-Bit SAR-ADC which is mainly used in electrocardiogram (ECG) measurement system. It is aimed for capturing the probability of arrhythmia through monitoring and recording ECG for a long period of time. Consequently, the power voltage was defined in 1V for low power consumption purpose. The chip was implemented by the TSMC 0.18μm 1P6M standard CMOS process technology. The sample rate is 600Hz in 150Hz signal bandwidth. Simulation results show that the SNDR and ENOB of the SAR-ADC with an input frequency of 24Hz are 67.53dB and 10.92dB. The power dissipation is 20.28μW under 1V power supply.
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