應用於動態多電壓調整之高效能低壓降線性穩壓器

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 學位論文 > Item 987654321/54196

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题名:	應用於動態多電壓調整之高效能低壓降線性穩壓器
其它题名:	High performance low dropout regulator for dynamic multi-voltage scaling application
作者:	沈宗模;Shen, Tsung-Mo
贡献者:	淡江大學電機工程學系碩士班楊維斌;Yang, Wei-Bin
关键词:	低壓降線性穩壓器;動態電壓調整;快速響應;LDO;DVS;Fast-transient response
日期:	2011
上传时间:	2011-06-16 22:08:49 (UTC+8)
摘要:	本篇論文以應用於動態電壓調整(Dynamic Voltage Scaling)之低壓降線性穩壓器，根據控制回授電路來決定輸出電壓的大小，相較於以往回授電路控制DC-DC Converter的方式，這種方式能大幅縮短穩壓時間並減少功率消耗。在運算放大器方面，採用Gm-C電路來增加系統開迴路增益，但會降低系統的穩定性，因此在負載電晶體的閘極與汲極間加上米勒補償(Miller Compensation)來穩定系統的相位以確保輸出電壓穩定。另外，為了大幅縮短多電壓切換時所需時間，提出一快速鎖定機制來針對低壓降線性穩壓器做快速穩壓，其設計重點在於，根據電流不同使得比較器的轉態點不同，這樣不僅能縮短穩壓時間也能減少晶片所需面積。因此，本篇論文以低壓降線性穩壓器根據回授電路的控制頻率或回授電阻的組合方式去降低/提高參考端的電壓準位以改變輸出電壓，並於電壓切換時透過快速鎖定機制去縮短穩壓時間並減少功率消耗，並針對運算放大器以及快速鎖定機制採用新架構設計，取代過去以回授電路控制DC-DC Converter的方式。過去動態電壓調整常用於回授控制DC-DC Converter來調整輸出電壓降低功率消耗，但鎖定電壓時間過久造成不必要的功耗常為人所詬病。因此本篇論文針對此問題，採用回授控制低壓降線性穩壓器的方式取代DC-DC Converter，此回授路徑較短鎖定時間也較快，故能有效減少功率消耗。 Power management IC is used to control the multi-voltage of portable electrical applications to power up many functional blocks. A low dropout (LDO) regulator usually provides a regulated power source for noise-sensitive blocks behind a switching DC-DC converter. The LDO can save power dissipation effectively owing to which possessing two output voltage, high and low, used in dynamic voltage scaling (DVS), not only that the LDO is extensively used due to its accuracy output voltage, low-noise, and fast transient response. However, it trends low voltage, low quiescent current and low dropout of LDO design now. In other words, the stability and performance of the LDO needs to be trade-off. The new dynamic fast settling low dropout regulator is presented for minimizing setting time in voltage switched by utilizing the Gm-C Operational Transconductance Amplifier (OTA) and fast-settling mechanism. The proposed LDO provides multiple discrete voltage levels of output by using multi-voltage control technique. Meanwhile, the settling time is reduced by utilizing dynamic fast-settling mechanism during output voltage switched. Furthermore, we propose the new comparator architecture to avoid the problems of overcharging and over-discharging at feedback node Vfb and output node Vout .The simulation results are based on 0.35μm CMOS process. The transient time of the proposed LDO is reduced from 4.2ms to 17μs. Moreover, the quiescent current of the Gm-C OTA circuit and fast-settling mechanism is 92μA in a heavy load condition.
显示于类别:	[電機工程學系暨研究所] 學位論文

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