高效能、低功率輸出緩衝放大器

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 學位論文 > Item 987654321/54193

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題名:	高效能、低功率輸出緩衝放大器
其他題名:	The high-performance and low-power dissipation output driver design
作者:	廖沛軒;Liao, Pei-Hsuan
貢獻者:	淡江大學電機工程學系碩士在職專班楊維斌
關鍵詞:	高效能;低功率;輸出緩衝放大器;High-Performance;Low-Power Dissipation;Output Driver
日期:	2011
上傳時間:	2011-06-16 22:08:22 (UTC+8)
摘要:	由於電腦相關產品產量一直持續成長，在日益重視節能減碳的環保環境條件下，電腦晶片皆以低功率消耗為發展目標。本論文提出之新型緩衝放大器可適用於電腦相關產品晶片設計上。其新型緩衝器具有二種緩衝放大器之特性，第一種特性是分離回授控制路徑CMOS緩衝放大器：是利用及回授輸出信號以切換分離路徑，並結合延遲單元以達到消除輸出短路電流功率消耗目的。第二種特性是拔靴式低電壓驅動器：主要是採用拔靴式(bootstrapped)大電容，提升MOSFET的交換速度，降低功率延遲乘積(Power-delay product)消耗。本論文之模擬環境以台灣積體電路公司0.35μm製程，與Intel ICH10 Chipset的時脈(14MHz、33MHz及48MHz)為主要模擬頻率，其模擬電壓條件為3.3V到1.8V(0.5V為一階)，模擬溫度條件為 -40℃到140℃ (10℃為一階)，此新型緩衝放大器與其他緩衝放大器在14MHz、33MHz及48MHz比較之下，在1.8V的功率延遲乘積比最好，其值分別為10.3%、10.8%、9.1%。 Due to the productivity growth of computer relevant products and based on the nowadays environment of respecting to the energy conservation, low power dissipation of computer chipset becomes one of the development goals. This paper is to address a new type of CMOS buffer which can be compatible in all the chipset design in computer relevant products. This new type of CMOS buffer has two main features. Firstly, this Feedback- controlled Split-path CMOS Buffer can distinguish the output signals, and then depart the path. In another words, it would eliminate the power dissipation of output short-current if the CMOS buffer has this inverted-delay-unit. Secondly, it has Bootstrapping Low-Voltage Driver features. This driver is to combine bootstrapping large capacitor to the MOSFET switch speed more than fast, it would eliminate the power-delay product dissipation. The simulated environment in this paper is based on the manufacture process of 0.35μm in TSMC and Intel ICH10 Chipset (14MHz, 33MHz and 48MHz) as main simulated frequency. The simulated range of voltage is from 3.3V to 1.8V (0.5V is the interval.). The simulated range of temperature is from -40℃ to 140℃ (10℃ is the interval.). As compared this CMOS buffer with others in 14MHz, 33MHz and 48MHz. At 1.8V this new type of CMOS buffer than the best of power-delay product dissipation and its value were 10.3%, 10.8%, 9.1%.
顯示於類別:	[電機工程學系暨研究所] 學位論文

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