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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/53887


    Title: 餘數碼產生器
    Authors: 李揚漢;賴宗弘;游榮豪;陳俊成;魏國純;陳禎祥
    Contributors: 淡江大學電機工程學系
    Date: 2001-09-01
    Issue Date: 2011-05-20 15:37:42 (UTC+8)
    Abstract: 本發明利用簡單之餘數碼結構,將輸入頻率與時脈作處理,並使用餘數碼產生器、餘數碼紀錄鑑別器搭配除頻器的計數裝置對特徵輸出值加以判斷鑑別,完成鑑別後輸出所對應頻率之數位編碼;此架構可以改善傳統中頻鑑頻器不易積體化,僅能接收窄波信號,耗電過大的缺點。此架構只需單一時脈為最大特色,且時脈至200KHz以下,並可以輕易達成M-ary FSK的設計,此結構可運用在 ERMES/FLEX系統規格之呼叫器中頻鑑頻器。此外,我們亦將餘數碼結構應用於頻率排序及偵測,使用餘數碼產生器、時間延遲電路、計數器、暫存器、比較電路以及最大最小值鑑別器,以構成頻率排序器及頻率偵測鑑別器。另外,我們亦使用平行架構之多時脈M-ary FSK鑑頻電路的技術,將M-ary FSK的訊號解調成數位信號加以辨識。其4-FSK符合ERMES/FLEX系統之規格。由於平行式多時脈又M-ary FSK鑑頻器電路架構簡單,推展至M-aryFSK其需k組 clock,及對應之k組平行式架構單時脈餘頻碼產生器,由於平行式的結構,其電路推動力與延遲時間,適合於在低電壓低功率電路之設計。
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Patent

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