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    題名: Design of a wideband RF transeeiver in a deep sub-micro CMOS process
    其他題名: 深次微米互補式金氧半製程之寬頻射頻接收發射器設計
    作者: 施鴻源;Shih, Horng-yuan
    貢獻者: 淡江大學電機工程學系
    關鍵詞: 射頻;接收發射器;寬頻;超寬頻;互補式金氧半製程;RF;Transceiver;Wideband;Ultra wideband;CMOS
    日期: 2010
    上傳時間: 2011-05-20 10:00:22 (UTC+8)
    出版者: 新竹市:交通大學電子工程學系
    摘要: This dissertation presents a wideband RF transceiver for ultra-wideband (UWB) applications implemented in a 1.2 V 0.13 μm CMOS process. The receiver design focuses on mode 1 of multi-band (MB) orthogonal frequency division multiplexing (OFDM) UWB (3~5 GHz) which is defined as essential band by WiMedia Alliance. The receiver chain is composed by a broadband 3~5GHz ESD-protected low-noise amplifier, a 3th-order notch filter, a current-mode down conversion mixer and a 250MHz wideband analog baseband. In the analog baseband, PGAs and filters are carried out by current-mode amplifiers to achieve wide bandwidth and wide dynamic range of gain, as well as low noise and high linearity. Besides, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers. A 6th-order Chebyshev low-pass filter realized in Gm-C topology is designed in the baseband chain for channel selection. Digitally-assisted DC-offset calibration improves second-order distortion of the entire chain. The entire receiver consumes 100 mW under a supply voltage of 1.2 V.
    In the design of transmitter, we attempt to cover both mode 1 and Band Group 3 of MB-OFDM UWB (3~8 GHz). The 3~8 GHz transmitter chain integrates an analog baseband, an in/quadrature-phase (IQ) modulator, a variable gain amplifier (VGA), a differential-to-single amplifier, a power amplifier, as well as a transmitted signal strength indicator (TSSI). The IQ modulator incorporates DC-offset cancellation circuits to improve carrier leakage suppression. This transmitter provides linear-in-dB output power tuning of 14 dB to fulfill the requirement of WiMedia UWB. Measured maximum output power and OP1dB are -5 dBm and +1.5 dBm, respectively. Measured carrier leakage suppression is over 40 dB after calibration. The high linearity and accurate IQ modulation lead to an error vector magnitude (EVM) of -28 dB under the data rate of 480 Mb/s in WiMedia Mode 1. The entire transmitter consumes 66 mW under a supply voltage of 1.2 V.
    本論文描述一以1.2 V 0.13 μm CMOS 製程實現,應用於超寬頻系統之寬頻射頻接收發射器設計。接收機設計在3~5 GHz 的頻段。整個接收機是由一3~5 GHz的寬頻低雜訊放大器、三階槽口濾波器、電流式的降頻混頻器與一頻寬為250 MHz之類比基頻電路所組成。在類比基頻的電路中,可變增益放大器與濾波器利用電流式放大器的形式設計達到寬頻、高增益動態範圍、低雜訊與高線性度之特點。此外一電流式Sallen-Key 低通濾波器被設計用來有效地濾除通道外的干擾訊號。一個六階的Chebyshev 低通濾波器被設計用來提供通道選擇。一數位輔助的直流偏移校正電路用來降低整個類比基頻電路的二階諧波失真。整個接收器電路在1.2 V 的操作電壓下消耗100 mW。
    在發射器的設計上,我們涵蓋3~8 GHz 的頻率範圍。整個發射器電路整合了一類比基頻電路、調變器電路、可變增益放大器、差動轉單端放大器與功率放大器,並整合了發射訊號強度指標電路。調變器電路並包括一直流偏移消除電路來增進其載波洩漏的抑制能力。整個發射器提供14 dB 的發射功率可調範圍,並具有-5 dBm的最大發射功率與+1.5 dBm 的輸出P1dB。藉由直流偏移消除電路可使得載波洩漏抑制達到40 dB。其高線性度與調變精準度使得在480 Mb/s 下EVM可達-28 dB,可滿足WiMedia Mode 1 的規格要求。整個發射器電路在1.2 V 的操作電壓下消耗66 mW。
    顯示於類別:[電機工程學系暨研究所] 學位論文

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