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    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/52830

    Title: The Hardware Design for a Genetic Algorithm Accelerator for Packet Scheduling Problems
    Authors: 李揚漢;Lee, Yang-han;詹益光;Jan, Yih-guang;曾憲威;Tseng, Hsien-wei;周允仕;Chou, Yun-hsih;Chuang, Ming-hsueh;Sheu, Shiann-tsong;莊岳儒;Chuang, Yue-ru;Shen, Jei-jung;Fan, Chun-chieh
    Contributors: 淡江大學電機工程學系
    Keywords: Genetic Algorithm;Packet Scheduling;Base Generator;Operation Selector;Delta Calculator;Duplicate Priority Encoder;Abort Priority Encoder;Next Generator
    Date: 2008-06-01
    Issue Date: 2010-12-01 10:37:12 (UTC+8)
    Publisher: 臺北縣:淡江大學
    Abstract: In the basic genetic algorithm and its variations, they usually process the calculations in a sequential way so that the waiting time for every generation member awaited to be processed increases dramatically when the generation evolution continues. Consequently the algorithm converging rate becomes a serious problem when we try to apply the genetic algorithm in real time system operations such as in the packet scheduling and channels assignment in the fiber optic networks.We first propose in this paper a genetic algorithm accelerator which has the capability not only to accelerate the algorithm convergent rate but also to have its solution to reach the problem's optimum solution. Then we develop hardware blocks such as the blocks of Base Generator, Operation Selector, Delta Calculator, Duplicate Priority Encoder, Abort Priority Encoder and Next Generator, etc. to realize this proposed generic algorithm accelerator. Due to these hardware blocks realizations it will enhance the speed of the algorithm converging rate and make certain its convergent solution reaches the problem's optimum solution.
    Relation: 淡江理工學刊=Tamkang journal of science and engineering 11(2),頁165-174
    DOI: 10.6180/jase.2008.11.2.08
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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