In recent years, computer applications have increased in the computational complexity. The speed requirement forces designers of general-purpose microprocessors to pay particular attention to implement the floating point unit (FPU). Anew floating-point division architecture that complies with the IEEE 754-1985 standard is proposed in this paper. This architecture is based on the New Svoboda-Tung (NST) division algorithm and radix-8MROR (maximally redundant optimally recoded) signed digit number system. In NST division, the dividend and divisor must be prescaled. For the divider implementation, a signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. A radix-8 MROR divider by TSMC 0.25 m technology is thus designed and simulated. The simulation results show that the performance, hardware cost, and power consumption of the proposed divider is competitive to the conventional SRT divider.
淡江理工學刊=Tamkang journal of science and engineering 11(2)，頁185-194