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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/52816

    Title: Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
    Authors: Rau, Jiann-Chyi;Wu, Po-han;Huang, Wnag-Tiao;Chien, Chih-Lung;Chen, Chien-Shiun
    Contributors: 淡江大學電機工程學系
    Keywords: Test Access Mechanism(TAM);Test Application Time;Core-Based SOCs
    Date: 2010-09-01
    Issue Date: 2010-12-01 10:35:07 (UTC+8)
    Publisher: 臺北縣:淡江大學
    Abstract: In this paper, we propose an algorithm based on a framework of reconfigurable multiple scan chains for system-on-chip to minimize test application time. The control signal combination causes the computing time increasing exponentially, and the algorithm we proposed introduces a heuristic control signal selecting method to solve this serious problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan chains. The results show that it could significantly reduces both the test application time and the computation time.
    Relation: 淡江理工學刊=Tamkang Journal of Science and Engineering 13(3),頁305-314
    DOI: 10.6180/jase.2010.13.3.10
    Appears in Collections:[電機工程學系暨研究所] 期刊論文

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