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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/52557


    Title: 使用低超取樣率實現一個時間交錯之高解析度三角積分調變器
    Other Titles: A high-resolution time-interleaved delta-sigma modulator with low oversampling rate
    Authors: 呂峻耀;Lu, Chun-yao
    Contributors: 淡江大學電機工程學系碩士班
    江正雄
    Keywords: 時間交錯;雜訊耦合;三角積分調變器;Time-interleaved;Noise-Coupled;Delta-Sigma Modulator
    Date: 2010
    Issue Date: 2010-09-23 17:55:03 (UTC+8)
    Abstract: 隨著各類電子產品輕薄短小的發展趨勢以及系統單晶片的特性,高速、高解析度及低功率消耗類比數位轉換器(Analog-to-Digital Converter, ADC)的設計變得更加困難,因此在設計電路時不僅需要解決降低功率消耗的問題,而且隨著先進製程的演變,電晶體越來越小,其漏電流的情況變得更加嚴重,導致應用在高速及高解析度的運算放大器(Operation Amplifier),必須加入更多其他電路來解決這些問題,增加了類比電路設計的困難。
    本篇論文提出了一個新的類比轉數位三角積分調變器(Delta-Sigma Modulator, DSM)架構,採用四組傳統回授二階串接的多位元三角積分調變器架構,以時間交錯(Time-interleaved)及雜訊耦合(Noise-coupled)的方法,將傳統單一操作頻率快速的路徑降低成四組只需傳統的四分之一低速路徑來實現。此外,此新架構還比傳統的二階架構多增加一階的雜訊移頻(Noise-shaping),並藉由運算放大器之增益來調整零點位置。使用此新架構不僅能降低運算放大器的需求,解決了類比電路的複雜度,並且在相同的訊號頻寬(Signal-Bandwidth)下,其解析度和輸入動態範圍(Input Dynamic Range)比傳統的單迴路串接高,而功率消耗也較低。
    實現上,以TSMC 0.18μm 1P6M 標準製程來實現電路,其工作電壓為1.8V,頻寬為25kHz,取樣頻率為3.2MHz,超取樣比為64。輸入動態範圍為104dB,而最大的訊號雜訊失真比為100.27dB,類比功率消耗為2.2mW,數位功率消耗為1.3mW,晶片面積為1.963μm×1.80048μm。
    As the proceeding progress of the CMOS process technique and the varieties of consumer electronic product requirements nowadays, the designs of high speed and high performance ADCs become very difficult. Due to the decreasing breakdown voltage of the gate, the leakage current condition becomes serious, and it results in requiring additional circuits for calibration.
    In this thesis we proposed a new four-channel second-order DSM with time-interleaved and noise-coupled techniques to improve the performance. This method not only decreases the speed to relax the opamps specification but increases the noise-shaping by one-order more. Besides, the system zero can be moved to optimize the system performance by the proposed technique of non-ideal opamps DC gain. The SNDR and dynamic range of the proposed DSM is better than that of the conventional single loop DSM with lower power dissipation.
    The chip was implemented by the TSMC 0.18μm 1P6M standard CMOS process technology. The post-simulation results indicate that this time-interleaved DSM has a SNDR of 100dB and a dynamic range of 104dB with 3.2MHz sampling rate in 25kHz signal bandwidth. The power dissipation of the proposed architecture is 2.2mW in the analog part and 1.3mW in the digital part under 1.8V power supply.
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Thesis

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