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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/52522


    Title: 以Avalon Bus技術支援MC8051同步化多重I/O控制應用於乙太網路控制器之實現
    Other Titles: Implementing multiple I/O and synchronous MC8051 to support ethernet controller base on Avalon Bus
    Authors: 吳秋宏;Wu, Chiou-hung
    Contributors: 淡江大學電機工程學系碩士班
    李維聰;Lee, Wei-tsong
    Keywords: Avalon匯流排;計算機結構;現場可編程輯閘陣列;矽智財核心技術;r微處理器;可程式化系統晶片;Verilog硬體描述語言;Avalon Bus;Computer Architecture;FPGA;IP Core;Microprocessor;SoPC;Verilog HDL
    Date: 2010
    Issue Date: 2010-09-23 17:52:36 (UTC+8)
    Abstract: 近年來,隨著嵌入式系統的發展,使得微控制器被廣泛的使用在不同的應用上,例如:智慧型手機、掌上型電腦、多媒體裝置、自動化系統、機器人控制等。針對嵌入式系統所設計的微控制器,是以控制功能與整合能力為第一優先考量。一般而言,微控制器會整合多元的通訊串列(UART、SPI、I2C、Microwire和1-wire等)、並列週邊(EMI、LBI和PCI Bus等)及一般輸出入介面(GPIO)等功能。而基於易使用、低成本、高頻寬與高穩定等特性,使得乙太網路在特定應用上是較為可行的傳輸方式,例如:即時影音傳輸、虛擬網路會議、高速資料傳送。因此,具備嵌入式網路功能的乙太網路微控制器,將成為未來的發展趨勢。
    目前國內的微控制器廠商在產品佈局方面,仍以8位元微控制器為主,其次為16位元。單就最典型的8位元微控制器MC8051,全球一年的出貨量就可高達33億顆。但由於傳統MC8051的程式記憶體(Program Memory)只有4K Byte、資料記憶體(Data Memory)只有128 Byte、4組I/O埠與內部單一匯流排等限制,使其操控性與擴充性一直無法被使用在複雜的網路控制上。
    因此本篇論文主要的研究是在於改進MC8051的4組I/O埠與單一匯流排限制,並使其能夠實現低成本、易操控與高擴充之乙太網路微控制器。為此目的,我們提出MC8051的等待狀態、ramx Transfer Interface與Ethernet Transfer Interface之設計。透過MC8051的等待狀態之設計,使得等待狀態可以插入MC8051的時序中,並使其保持閒置。而ramx Transfer Interface之設計,使得MC8051外部資料記憶體模組的控制訊號與Avalon匯流排可以互相結合。藉由Avalon的同步與共享機制,使得MC8051可以實現同步化多重I/O之控制。而Ethernet Transfer Interface之設計,使得MC8051同步化多重I/O控制可以整合DM9000A乙太網路控制器,並實現其乙太網路之控制能力。根據封包處理速率之分析結果,可以發現對於家電控制、工業控制、自動化系統、遠端管理與環境監控等基本網路控制,並不會牽扯到過於複雜的封包交換程序。因此,經由我們的MC8051封包處理速率分析,我們的研究確實有其可行之處。
    In recent years, with the process of embedded systems, microprocessors have been widely used on many applications such as smart phones, laptops, multi-media equipments, automatic control systems, robot controls, etc. For the microprocessors designed for embedded systems, it firstly considers the control capability and integration capability. In general, the microprocessor integrals many communication sequences (e.g., UART, SPI, I2C, Microwire, 1-wire), parallel peripherals (e.g., EMI, LBI, PCI Bus) and General Purpose I/O (GPIO). Ethernet network always is an applicable transmission method in certain applications such as real-time multi-media transfer, virtual network conference, high speed data transfer, etc. because of its easy to use, low cost, high bandwidth and high stability. In conclusion, the embedded Ethernet micro-controller is one of the future trends.
    Nowadays, the 8 bits micro-controllers still are the main product in Taiwan, and the 16 bits micro-controllers are the second one. The most typical 8 bits micro-controller is MC8051, because it sells 3.3 thousand million ones averagely in one year. MC8051 owns program memory with 4k bytes, data memory with 128 Bytes, 4 sets I/O ports and one single bus, so it can never be used to the application of controlling internet.
    Our search is to improve the limitation casing by the 4 sets I/O ports and one single bus in MC8051 and implement an Ethernet micro-controller which is low cost, easy to use and high adaptability. We proposed the Waiting State of MC8051 and two circuits called ramx Transfer Interface and Ethernet Transfer Interface, respectively. The waiting state can be inserted into the timing of MC8051 and keeps an idle state though the design of the Waiting State for MC8051. The control signals of external data memory model of MC8051 can be combined with Avalon bus though the design of ramx Transfer Interface. The synchronous and shared mechanism of Avalon allows MC8051 to realize synchronous and multiple I/O control. Then the synchronous and multiple I/O control can be integrated with DM 9000A Ethernet controller and realize the control capability of Ethernet through the design of Ethernet Transfer Interface. According to our analysis of packet processing rate, our contribution can be used to basic network control (e.g., electric appliances, industry control, automatic control systems, remote management, Environmental Monitoring) because it does not require too complicated packet handshake procedure. With our analysis of packet processing rate, we truly proposed a feasible study in some respects.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

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