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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/52518

    Title: 基於SoPC之交通標誌偵測與辨識
    Other Titles: SoPC-based traffic sign detection and recognition
    Authors: 陳銘燿;Chen, Ming-yao
    Contributors: 淡江大學電機工程學系碩士班
    易志孝;Yih, Chi-hsiao
    Keywords: 類神經網路;霍夫轉換;交通標誌偵測;交通標誌辨識;SoPC;Neural Network;Hough Transform;traffic sign detection;Traffic Sign Recognition;SoPC
    Date: 2010
    Issue Date: 2010-09-23 17:52:28 (UTC+8)
    Abstract: 本論文『基於SoPC之交通標誌偵測與辨識』之設計方式為利用多主從系統架構設計為基礎,在FPGA晶片內設計多個主控端硬體加速模組搭配Nios II處理器來實現。整個系統架構規劃為三大部份:(1)交通標誌偵測(Traffic Sign Recognition) 、(2)交通標誌辨識(Traffic Sign Recognition)及(3)動態影像擷取。主要功能為利用CMOS影像感測器偵測交通標誌,透過線上訓練類神經網路晶片(On-line Training of Neural Network Chip)將擷取之標誌分類,確定時速條件且判斷車輛是否違反標誌限制,使得修正車輛行駛方向或採取減速保持安全,避免意外事故發生。本系統擬使用軟硬體協同設計的方法,並且以較低成本開發較高級複雜演算法及較高效能的方式來設計實現駕駛輔助系統。類神經網路(Neural Network)在影像分類上有很好的表現,並且數學模型容易用硬體實現,希望突顯硬體加速器的優勢,發展出可線上學習的類神經電路,實現於Altera FPGA 開發版。如此一來,不但可以提升訓練與辨識效能,有效降低學習時間,再搭配即時動態影像,使得系統盡量滿足駕駛輔助系統在影像上的應用必須要即時(Real-Time)的特點。並且從實驗結果可以驗證所提之軟硬體共同設計確實可以用較少的影像處理時間達到即時的訓練與辨識。
    In this thesis, an intelligent traffic sign detection and recognition system is designed and implemented on an FPGA platform based on a multiple master-slave system architecture to achieve the goals of traffic sign detection and recognition. The whole system is divided into three parts: (1) dynamic image capture, (2) traffic sign detection, and (3) traffic sign recognition. From the images captured by the CMOS image sensor, the traffic sign in the obtained image is detected through a series of image processing steps. The resultant image is further classified by a multilayer neural network with the backpropagation learning algorithm. The results of the neural network based classifier can be used to regulate the speed of car for safety and command certain actions to avoid accidents. The IDAS is realized by taking the software/hardware co-design approach which not only saves cost but also increases efficiency. To fully take advantages of hardware accelerators and satisfy the need of real-time image recognition, a very large integrated circuit (VLSI) is designed specifically for the on-line training of neural networks. Our experimental results show that hardware/software co-design approach can effectively reduce the learning time of neural networks.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

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