隨著無線網路與可攜式電子產品的流行，近年來類比/數位轉換器皆朝著高頻寬、高解析度及低功耗的目標邁進。相較於離散時間架構的類比/數位轉換器，連續時間架構的類比/數位轉換器將擁有較低的功耗，但是複雜的數學計算過程將增加設計難度。而隨著製程不斷的演進，越來越低的供應電壓與越來越嚴重的漏電情形，增加了類比電路設計的困難。因此如何簡化連續時間架構的類比/數位轉換器的設計流程與類比複雜度將成為為本篇論文的目標。 本篇論文提出了一個新的連續時間類比/數位三角積分調變器(Delta-sigma Modulator)架構，有別於傳統從離散架構轉換至連續時間架構時，必須增加類比補償路徑或重新設計數位濾波器端，新的架構將類比補償路徑移至數位濾波器實現，並且不須重新設計數位濾波器，新的架構將簡化設計所包含的數學運算或類比電路複雜度。 本論文主要的研究方向為設計一個適用於GSM/WCDMA/WiMAX的連續時間三角積分調變器。其中電路設計的部份，在較低速的操作模式時，將關閉部分電路以達到減少功耗的目標。以TSMC 90nm 1p9m 標準製程來完成前模擬，其工作電壓為1.2V，頻寬分別為100k/2M/10M Hz，取樣頻率為分別為40M/160M/320M Hz，超取樣率為200/40/16。而最大的訊號雜訊失真比分別為85/70/61 dB，功率消耗則分別為4/6.4/15 mW。而在實現部分與後模擬部分，因為考量到電容和電阻的偏異必須增加額外的調整電容，在晶片面積與成本的考量下只實現WiMAX的規格。 With wireless networks and portable electronic products popularized in recent years, the goals of analog-to-digital converter (ADC) are gradually moving into the trend of high bandwidth, high resolution, and low power consumption. To contrast continuous-time (CT) architecture with discrete-time (DT) architecture, the CT architecture consumes less power than that of the DT architecture. Due to the complex derivation of mathematics, it is difficult to design a proper CT architecture. With the evolution of VLSI process technology, both the lower supply voltage and leakage current increase the difficulties of analog circuit design. This thesis tries to simplify the structure of CT ADC and analog part complexity of the design. We present a new architecture of CT analog-to-digital delta sigma modulator (DSM) in this thesis. Differing from the traditional method to design a CT DSM from the DT DSM needs to increase analog compensation paths or re-design the digital filters, the new approach uses digital filters to replace the analog compensation paths without re-designing digital filters. The new method simplifies the design procedural and induces the analog circuit complexity. This research tries to design a CT DSM for GSM / WCDMA / WiMAX applications. When operating at low speed mode, it will shut down the part of the circuit to save power. The circuit is designed by the TSMC 90nm 1p9m standard process; the supply voltage is 1.2V; bandwidths are 100k/2M/10M Hz; sampling frequencies are 40M/160M/320M Hz; oversampling rates(OSR) are 200/40/16. The greatest signal to noise distortion ratio are 85/70/61 dB, and the power consumptions are 4/6.4/15 mW(pre-simulations). In the implementation and post-simulations, because of the problems of RC-variation must be additional adjustments capacitors, the chip size and cost will increase, we only present WiMAX specifications.
